Overview

Job Overview:

We are looking for Lead FPGA / Embedded-Systems Engineer to join Arm’s Solution Engineering Hardware Platforms team on a permanent basis. The team is based in Cambridge and Manchester, UK working at the forefront of Arm based embedded design.

 

We are a multi-disciplinary team with software, FPGA and board design expertise delivering platforms internally and externally in support Arm’s IP business model. This role will initially involve leading a FPGA design team to prototype and validate new FPGA hardware platforms and develop reference design material.

 

The team creates physical hardware development platforms based around Arm’s leading CPU and system IP solutions. These platforms are used for software development and IP validation activities both internally by Arm and externally by partners/customers.

 

You’ll be the lead, generating the FPGA prototype design for enablement and validation, working with software and boards engineers. Responsibilities for engineering release flows with a strong focus on engineering efficiency and quality.

The role includes RTL creation and modification along with implementation constraints with high-quality, clear, accurate technical documentation. Familiarity with writing and reviewing documentation is desirable.

 

The successful candidate will be responsible for delivery of designs using techniques such as gated clock conversion and synthesizable models to build accurate representations of real-world systems.

Responsibilities:

  • Leading and mentoring a team of engineers.
  • Liaise and collaborate with development teams, translating high level requirements into project and design requirements, ensuring these are implemented and where not possible/feasible providing mitigations and alternatives.
  • Breaking down the requirements (technical and delivery) and translating into packages of work that are direct inputs in forming a resourced project plan.
  • Tracking to the project plan, identifying, and managing risks and reporting status
  • Developing FPGA implementations targeting both our internal platforms and 3rd party platforms to demonstrate Arm’s latest IP products.
  • Commissioning of FPGA prototyping hardware including specification of peripheral hardware.

Required Skills and Experience:

Solid FPGA Engineer with strong technical leadership skills are important for this role! Development of accurate project plans involving multiple teams and ensuring deliveries follow the agreed plan. Design automation is critical when constructing efficient design and delivery flows, scripting skills in Python and TCL would be advantageous.

  • Detailed knowledge of the FPGA design flow from RTL design, simulation, synthesis and place & route.
  • Demonstrate an understanding of ASIC/SoC prototyping in FPGA.
  • Strong RTL skills in Verilog / System Verilog or VHDL.
  • Excellent communications skills, written and spoken English; ability to write coherent documentation.

“Nice To Have” Skills and Experience:

  • Knowledge and expertise in debugging sophisticated designs, embedded software, simulation and hardware.
  • A creative and structured approach to problem-solving.
  • Working with the latest Xilinx UltraScale+ devices and tools.
  • Use of Synplify tool chain for single FPGA implementations.
  • Knowledge/Experience of implementation of DDR memory sub-systems.
  • Programming languages such as: assembly language (ideally Arm assembler), higher-level (e.g. C), object-orientated (e.g. C++)
  • Use of a UNIX environment and shell programming/scripting in e.g. Tcl, Perl, Python etc.
  • Experience and knowledge of Arm IP and AMBA standard.

In Return:

You will get to expand your expertise, be challenged and work with advancing technologies. Working alongside many other engineering teams including software, IP implementation and verification involving deep technical discussions, working with top class multifunctional engineering teams.

 

#LI-SM1

This job was originally posted as: https://click.appcast.io/track/jtse5g8?cs=pe7&jg=7643&bid=_ourD5Y9adGWgFOjps_shQ==